Moore’s Law, named after Intel’s former CEO Gordon Moore, means that the number of transistors in an integrated circuit doubles every two years. For 55 years, the semiconductor industry has used Moore's Law to formulate roadmaps and R&D goals.
In order to continue Moore's Law and realize the miniaturization of chips, new technologies have continued to emerge in 55 years. But historically, the photomask of the wafer has limited the maximum size of a single chip, and chip manufacturers and designers have had to use multiple chips to complete the provided functions. In many cases, even multiple chips provide the same function, just like the core of the processor and the memory module.
The SoC (System on Chip) technology that has been used before can combine different modules, and the communication between the modules is faster, while the power consumption is lower, the density is higher, and the cost is lower. However, in recent years, the cost of advanced manufacturing nodes has increased, weakening the cost advantage of SoC technology.
At the latest TSMC 2021 Open Innovation Platform event, Alchip Technologies’ vice president of R&D James Huang said that Chiplet’s “small chips” and advanced packaging technology can provide a more competitive cost structure than a single SoC, while maintaining close performance and functionality. Consumption.
It cited two technologies that are critical to the development of small chips/packages: one is TSMC’s 3DFabric and CoWos combination technology, and the other is Alchip’s APLink die-to-die (D2D) I/0 technology.
Chiplet "small chip" technology, as the name suggests, is to package multiple small chips together, and use die-to-die internal interconnection technology to form heterogeneous System in Packages (SiPs) chips. The smaller chip monomer can increase the utilization rate of each wafer, thereby reducing costs.
But in order to maintain Moore's Law, Chiplet "chiplet" technology also needs to provide performance close to that of SoC technology , and AIchip's APLink D2D I/0 technology is required to support high-speed data flow between multiple small chips.
APlink 1.0 uses TSMC’s 12nm process with a speed of 1Gbps; APlink 2.0 uses a 7nm process with a speed of 4Gbps; APLink 3.0 under test already has a speed of 16Gbps.
According to the roadmap, the upcoming APLink 4.0 will use the 3nm D2D process. APlink 4.0 IP will support north/south, east/west directions and symmetrical PHY alignment to minimize D2D line length. The I/O bus of its interconnect topology will use standard core voltage, and the PHY macro speed will reach 12Tbps. The speed of each DQ reaches 16Gbps with only 5 nanoseconds delay.
Chiplet "small chip" technology involves packaging, EDA, chip architecture design and other fields, and there is also an opportunity to restructure the semiconductor industry chain. But the key to the final landing is the business model, and Chiplet’s "small chip" still needs some time to prove itself.
0 Comments