The research and development of the third-generation Xiangshan RISC-V open source processor core of the Chinese Academy of Sciences was launched

Bao Yungang, a researcher at the Institute of Computing Technology, Chinese Academy of Sciences, announced that on August 24, 2022, the Institute of Computing Technology of the Chinese Academy of Sciences, Beijing Open Source Chip Research Institute, Tencent, Ali, ZTE, Thundersoft, Yi Siwei, Suineng, etc. formed a joint R&D team to carry out the joint development of the third-generation Xiangshan (Kunming Lake architecture) .

Xiangshan uses lakes to name each generation of architecture - the first generation architecture is Yanqi Lake, the second generation architecture is Nanhu Lake, and the third generation architecture is Kunming Lake. The Xiangshan open source community said that the first-generation "Yanqi Lake" architecture has been successfully taped out , and the actual measurement has reached the expected performance , and the second-generation "Nanhu" architecture is being continuously iteratively optimized.

Xiangshan is an open source RISC-V processor core. "Nanhu" adopts SMIC's 14nm process, the target frequency is 2GHz , and the SPECCPU score reaches 10 points/GHz. It supports dual-channel DDR memory and PCIe, USB, HDMI, and more.

According to reports, one of the important decisions for the development of the "Xiangshan" processor core was the choice of the agile design language Chisel, because the development efficiency is much higher than Verilog, and the code size of Chisel is only 1/5 of Verilog.

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