TSMC research general Dr. Mi Yujie revealed that TSMC will obtain ASML's next-generation extreme ultraviolet lithography equipment (high-NA EUV) in 2024 to develop related infrastructure and architecture solutions for customers. Program.
Zhang Xiaoqiang, vice president of business development at TSMC, said before that after obtaining the equipment, it was mainly used for joint research with partners in the initial stage.
Judging from the previously announced information, the unit price of High-NA EUV lithography equipment is estimated to be 400 million US dollars (about 2.8 billion yuan), which is two or three times that of existing EUV lithography equipment.
Samsung Electronics Vice Chairman Lee Jae-Yong had previously held talks with ASML on the introduction of the Dutch semiconductor equipment manufacturer's next-generation extreme ultraviolet (EUV) lithography equipment and discussed the introduction of EUV lithography equipment produced this year. The equipment and the high numerical aperture (High-NA) EUV lithography equipment planned to be launched next year have reached an agreement.
Earlier this year, Intel also announced that it had signed a contract to purchase five of these devices (TWINSCAN NXE:3600D) to produce 1.8-nanometer chips in 2025. TSMC also said at the Silicon Valley Technology Symposium on June 16 that it will introduce High-NA EUV lithography equipment into its process for the first time in the world in 2024.
For now, advanced lithography is a key factor in measuring the upper limit of chip manufacturing, and this High-NA lithography is expected to reduce the size by 66%. In the field of chip manufacturing, although the current 3nm and 5nm no longer represent the actual gate width, the smaller the better.
It is reported that this new EUV system can achieve a 0.55 numerical aperture, compared with the previous EUV system (TWINSCAN NXE:3400B and NXE:3400C) equipped with a 0.33 numerical aperture lens, the accuracy will be improved, and higher resolution patterns can be achieved change.
It is reported that the current cost of ASML per machine is as high as 160 million US dollars, and the major chipmakers also plan to invest more than 100 billion US dollars in the construction of additional manufacturing plants in the next few years to meet further semiconductor demand.
Officials have revealed that this High-NA machine will be 30% larger than the existing machine, and the previous machine was so large that it even required three Boeing 747s to load them.
TSMC previously announced that its goal is to mass-produce its N2 process in 2025. Unlike the 3nm process node, the 2nm process node will use Gate-all-around FETs (GAAFET) transistors, which TSMC claims will be 10% to 15% compared to the 3nm process. % performance improvement, and can also reduce power consumption by 25% to 30%. The N2 process is expected to be ready for risk production in late 2024 and enter high-volume production in late 2025, with customers receiving their first chips in 2026.
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