Samsung is planning to use a technology called Backside Power Supply Network (BSPDN) to develop 2nm, which was actually just last week by researcher Park Byung-Jae at Samsung. New technology was introduced at SEDEX 2022.
In a nutshell, this approach gives an alternative to process indentation and 3D packaging: developing the backside of the wafer.
In the foundry market, technology is evolving from high-k metal gate planar FETs to FinFETs to MBCFETs and now BSPDNs, Park said.
Eric Beyne, Senior Fellow, Vice President of R&D, and Program Director of 3D Systems Integration at Imec, said: "A chiplet involves a chiplet that is individually designed and processed. A well-known example is high-bandwidth memory (HBM) - also known as dynamic random access. A stack of memory (DRAM) chips. This memory stack is connected to the processor chip through an interface bus, which limits its use to latency-tolerant applications. As a result, the chiplet concept will never allow fast access to and from mid-level cache memory."
With 3D-SOC integration, we can implement logical partitioning of memory using direct and shorter interconnects, resulting in significantly improved performance. In the paper, the authors show an optimized implementation of a 3D-SOC design with memory macros at the top of the Die and the rest of the logic at the bottom of the Die a full 40% increase in operating frequency compared to a 2D design.
One possible partition of a high-performance 3D-SOC system involves placing some or all of the memory macros at the top of the Die and logic at the bottom of the Die.
On the technical side, this can be achieved by bonding the active front side of the "logic wafer" to the active front side of the "memory wafer" using low-temperature wafer-to-wafer bonding. In this configuration, the original backsides of both wafers are now outside the 3D-SOC system.
Eric Beyne said: “We can now consider utilizing the 'free' backside of these chips for signal routing or directly powering transistors in the 'logic wafer'. Traditionally, signal routing and power delivery have occurred on the front side of the wafer, where they are Competing for space in complex back-end interconnect schemes. In these designs, the backside of the silicon is used only as a carrier. In 2019, Arm's simulations showed for the first time the beneficial effects of using BSPDN in a CPU) design implemented by imec Developed 3nm process. In this design, the interconnect metal on the backside of the wafer thinning is connected to the 3nm transistors on the front side of the silicon wafer using through-silicon vias (TSVs) on buried power rails.
Therefore, additional performance gains can be expected when the BSPDN is implemented to provide power-hungry core logic at the bottom of a "logic memory" 3D-SOC. Alternative 3D-SOC partitions can also be considered, where some memory blocks, such as L1-level cache static random access memory (SRAM), are also in the bottom die, also powered from the backside.
In addition to expanding the possibilities of 3D-SOC designs, BSPDN has also been proposed for monolithic single-chip logic and SRAM system-on-chip (SOC), which can aid further device and IC expansion.
Geert Van der Plas, project manager at imec, said: "Moving the power supply network to the backside of the silicon has proven to be an interesting approach to address back-of-the-line (BEOL) routing congestion challenges and reduce IR drop. This is a very similar approach to the 3D-SOC approach. The main difference is that the dummy wafer is now bonded to the target wafer for backside wafer thinning and metallization." One of imec's partners announced at the time that it would be implemented in one of its future node chips Such as a BSPDN concept.
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