China Launches Domestic Chiplet Technology Standard

China has released its first native chiplet technology standard, according to reports from the Second China Interconnection Technology and Industry Conference. The "Small Chip Interface Bus Technical Requirements" standard was developed by a group of integrated circuit experts and approved by the China Electronics Industry Standardization Technology Association of the Ministry of Industry and Information Technology.

Chiplets, also known as modular chip design or heterogeneous integration, involves the use of multiple smaller chips or chiplets to create a larger, more complex chip. These chiplets are designed to perform specific functions and can be combined in various ways to create custom chips with the desired capabilities.

The "Small Chip Interface Bus Technical Requirements" standard provides technical guidance for the use of chiplet technology in a variety of application scenarios, including CPUs, GPUs, artificial intelligence chips, network processors, and network switching chips. The standard covers a range of technical requirements for the chiplet interface bus, including a general overview, interface requirements, link layer, adaptation layer, physical layer, and encapsulation requirements. These requirements are intended to ensure that chiplets can be used effectively and reliably in various application scenarios, and that they can be seamlessly integrated into the larger chip systems in which they are used.

The adoption of chiplet technology allows for more efficient and flexible chip design and production, as it enables manufacturers to reuse existing chiplets rather than designing and producing entirely new chips from scratch for each new application. This can reduce the cost and time required to bring new chips to market and can also enable the creation of chips with a wider range of capabilities and performance levels. The "Small Chip Interface Bus Technical Requirements" standard will likely enable Chinese chipmakers to more easily adopt and integrate chiplet technology into their design and production processes, and may also encourage the development of new chiplet-based products and applications within the country.

The standard identifies several application scenarios for chiplet technology, including C2M (Computing to Memory), the interconnection between computing chips and memory chips; C2C (Computing to Computing), the interconnection between computing chips; C2IO (Computing to IO), the interconnection between computing chips and IO chips; and C2O (Computing to Others), the interconnection between computing chips and other small chips such as signal processing and baseband units. The standard lists three types of interfaces, including parallel bus, and outlines various speed requirements. It also defines the layers and physical layer of the chiplet interface and supports the use of existing protocols such as PCIe, as well as listing requirements for packaging methods. The design of small chips can make use of both international advanced packaging methods and domestic packaging technology.

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